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1/11 tda7467 november 2003 n 1 stereo input n input attenuation control in 0.5db n step C mute function n mono mode (srs 3d mono) n stereo mode (srs 3d stereo) n space and center attenuators are available n all function are programmable via serial bus (i 2 c bus) description the tda7467 is a srs (sound retrieval system) audio matrix. it reproduces srs sound processing stereo and mono sources both. the srs sound is guaranteed by external compo- nents and it is not affected by internal process spreads. the ac signal setting is obtained by resistor net- works and switches combined with operational amplifiers according to the srs labs specification. control of all the functions is accomplished by se- rial bus. thanks to the used bipolar/cmos/ dmos technology, low distortion, low noise and dc stepping are obtained. dip28 so28 ordering numbers: tda7467 tda7467d audio matrix with srs effects pin connection (top view) addr sda agnd ps1 ps2 ps4 ps3 ps5 ps6 1 3 2 4 5 6 7 8 9 netw1 netw2 vrefout hp2 hp1 hp3 v s hp4 hp5 23 22 21 20 19 17 18 16 15 d96au507 10 11 12 13 14 28 27 26 25 24 lout rin lin dig_gnd scl hp6 lp1 lp2 cref rout the device incorporates the srs (sound retrieval system) under licence from srs labs, inc.
tda7467 2/11 block diagram l-in mono 0.15 m f supply v s agnd cref 1 m f hp1 0.1 m f d96au506 i 2 c bus decoder + latches scl sda addr r-out l-out 22 m f - ps1 phase shifter 2 srs ps2 ps3 100nf ps4 3 21 8 27 18 20 5 7 6 2 0.15 m f 31.5db control r-in 31.5db control 0.47 m f netw2 netw1 2 15 16 srs fix mono 50k 50k center space 1k 4.42k 0.47 m f 1.5k 32.4k 130k 47.5k 4.7nf 3.74k vrefout 17 v ref fix + 15nf ps5 2.2nf ps6 27nf 4.7nf 0.47nf phase shifter 1 + - mix mix + hpf1 19 hp2 hp3 1 m f hp4 0.1 m f 22 24 hpf2 23 hp5 hp6 lpf1 1 m f 0.1 m f lp1 lp2 + srs + + + mono 12 13 14 9 10 11 25 26 1 dig_gnd 4
3/11 tda7467 thermal data absolute maximum ratings quick reference data symbol parameter value unit r th j-pins thermal resistance junction-pins max. 85 c/w symbol parameter value unit v s operating supply voltage 11 v t amb operating ambient temperature -10 to 85 c t stg storage temperature range -55 to +150 c symbol parameter min. typ. max. unit v s supply voltage 7 9 10.2 v v cl max. input signal handling 2 vrms thd total harmonic distortion v = 1vrms f = 1khz 0.01 0.1 % s/n signal to noise ratio v out = 1vrms (mode = off) 106 db s c channel separation f = 1khz 90 db input control (0.5db) -31.5 0 db srs center control (1db step) -31 0 db srs space control (1db step) -31 0 db mute attenuation 100 db electrical characteristcs refer to the test circuit t amb = 25c, v s = 9v, r l = 10k w , v in = 1vrms; r g = 600 w , all controls flat (g = 0db), effect ctrl = -6db, mode = off; f = 1khz unless otherwise specified symbol parameter test condition min. typ. max. unit supply v s supply voltage 7 9 10.2 v i s supply current 25 ma svr ripple rejection l ch / r ch out , mode = off 60 80 db input stage r in input resistance 37.5 50 62.5 k w v cl clipping level thd = 0.3% 2 2.5 vrms a vmin min. attenuation -1 0 1 db a vmax max. attenuation 31 31.5 32 db a step step resolution -1 0.5 1 db v dc dc steps adjacent att. step -3 0 3 mv srs effect control c range1 center/space control range -31 0 db s step1 center/space step resolution 1 db
tda7467 4/11 audio outputs n o(off) output noise (off) output muted, flat bw (20hz to 20khz) 4 5 m vrms m vrms n o(srs) output noise (srs) surround sound bw (20hz to 20khz) 50 m vrms d distortion a v = 0; v in = 1vrms 0.01 0.1 % s c channel separation 90 db v ocl clipping level d = 0.3% 2 2.5 vrms r out output resistance 30 w v out dc voltage level 3.8 v bus inputs v il input low voltage 1v v ih input high voltage 3 v i in input current -5 5 m a v o output voltage sda acknowledge i o =1.6ma 0.4 v srs surround sound matrix cente r srs control range -31 0 db step c center step resolution 1 db space srs space control range -31 0 db step s space step resolution 1 db p ersp1 perspective 1 input signal of 125hz space = 0db, center = mute r in = gnd; l in ? r out 12 db p ersp2 perspective 2 input signal of 2.15khz space = 0db, center = mute r in = gnd; l in ? r out 0db l+r l+ r srs curve space = 0db, center = mute r in = gnd; l in ? r out -8.5 db l, r l, r srs curve space = 0db, center = mute r in = gnd; l in ? l out l in = gnd; r in ? r out -13.4 db electrical characteristcs (continued) refer to the test circuit t amb = 25c, v s = 9v, r l = 10k w , v in = 1vrms; r g = 600 w , all controls flat (g = 0db), effect ctrl = -6db, mode = off; f = 1khz unless otherwise specified symbol parameter test condition min. typ. max. unit
5/11 tda7467 i 2 c bus interface data transmission from microprocessor to the tda7467 and vice versa takes place through the 2 wires i 2 c bus interface, consisting of the two lines sda and scl (pull-up resistors to positive supply voltage must be connected). data validity as shown in fig. 1, the data on the sda line must be stable during the high period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. start and stop conditions as shown in fig.2 a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high transition of the sda line while scl is high. byte format every byte transferred on the sda line must contain 8 bits. each byte must be followed by an acknowledge bit. the msb is transferred first. acknowledge the master ( m p) puts a restive high level on the sda line during the acknowledge clock pulse (see fig. 3). the peripheral (audio processor) that acknowledges has to pull-down (low) the sda line during this clock pulse. the audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the sda line remains at the high level during the ninth clock pulse time. in this case the master transmitter can generate the stop information in order to abort the transfer. transmission without acknowledge avoiding to detect the acknowledge of the audio processor, the m p can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. this approach of course is less protected from misworking. figure 1. data validity on the i 2 cbus figure 2. timing diagram of i 2 cbus figure 3. acknowledge on the i 2 cbus sda scl data line stable, data valid change data allowed d99au1031 scl sda start i 2 cbus stop d99au1032 scl 1 msb 23789 sda start acknowledgment from receiver d99au1033
tda7467 6/11 software specification interface protocol the interface protocol comprises: n a start condition (s) n a chip address byte n a subaddress bytes n a sequence of data (n byte + acknowledge) n a stop condition (p) ack = acknowledge s = start; p = stop a = address b = auto increment examples no incremental bus the tda7467 receives a start condition, the correct chip address, a subaddress with the msb = 0 (no incremental bus), n-data (all these data concern the subaddress selected), a stop condition. incremental bus the tda7467 receive a start conditions, the correct chip address, a subaddress with the msb = 1 (incre- mental bus): now it is in a loop condition with an autoincrease of the subaddress whereas subaddress from "1xxxx1xx" to "1xxx111" of data are i gnored. the data 1 concern the subaddress sent, and the data 2 concerns the subaddress sent plus one sent in the loop etc, and at the end it receivers the stop condition. s 1 0 0 0 0 0 a 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d96au420mod b data subaddress data 1 to data n s 1 0 0 0 0 0 a 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d96au421mod 0x subaddress data xxx xd1d0 s 1 0 0 0 0 0 a 0 ack ack data ack p msb lsb msb lsb msb lsb chip address d96au422mod 1x subaddress data 1 to data n xxx xd1d0
7/11 tda7467 data bytes (address = 80(hex) if addr pin is floating, 82(hex) if addr pin is connected to vs): function selection: the first byte (subaddress ) b = 1: incremental bus; active b = 0: no incremental bus x = indifferent 0, 1 input attenuation selection input attenuation = 0 ~ -31.5db srs mode recommended to attenuate -3db on "srs off" ie. mono srs (mono 3d): xxxxxx01 msb lsb subaddress d7 d6 d5 d4 d3 d2 d1 d0 bxxxxx0 0mode bxxxxx0 1srs/space attenua tion bxxxxx1 0srs /center attenuation bxxxxx1 1input attenuation msb lsb input attenuation d7 d6 d5 d4 d3 d2 d1 d0 0.5 db steps 000 0 001 -0.5 010 -1 011 -1.5 100 -2 101 -2.5 110 -3 111 -3.5 4 db steps 0000 0 0001 -4 0010 -8 0011 -12 0100 -16 0101 -20 0110 -24 0111 -28 1 mute d7 d6 d5 d4 d3 d2 d1 d0 mode x 0 srs off (fix) x 1 srs on 0 1 mono srs (mono 3d) 1 1 stereo srs (stereo 3d)
tda7467 8/11 space & center attenuation selection x = indifferent 0, 1 space & center attenuation = 0db ~ -31db power on reset msb lsb space & center att. d7 d6 d5 d4 d3 d2 d1 d0 1 db steps 000 0 001 -1 010 -2 011 -3 100 -4 101 -5 110 -6 111 -7 8 db steps 000 0 001 -8 0 1 0 -16 0 1 1 -24 1xxxxx mute input mute mode off (fix) space attenuation mute (min) center attenuation mutr (min)
9/11 tda7467 dim. mm inch min. typ. max. min. typ. max. a1 0.63 0.025 b 0.45 0.018 b1 0.23 0.31 0.009 0.012 b2 1.27 0.050 d 37.34 1.470 e 15.2 16.68 0.598 0.657 e 2.54 0.100 e3 33.02 1.300 f 14.1 0.555 i 4.445 0.175 l 3.3 0.130 dip28 outline and mechanical data
tda7467 10/11 so28 dim. mm inch min. typ. max. min. typ. max. a 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 c 0.5 0.020 c1 45 (typ.) d 17.7 18.1 0.697 0.713 e 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 f 7.4 7.6 0.291 0.299 l 0.4 1.27 0.016 0.050 s8 (max.) outline and mechanical data
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com 11/11 tda7467

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